FACULTY

Complex SoCs contain dozens of components made of processor cores, DSPs, memory, accelerators, and I/O, all integrated into a single die area of just a few square millimeters. Such complex systems will be interconnected via a complex on-chip interconnect closer to a sophisticated network than current bus-based solutions. This network must provide high throughput and low latency while keeping area and power consumption low. Our research effort is about solving several design challenges to enable such new paradigm in massively parallel many-core systems. In particular, we are investigating fault-tolerance, 3D-TSV integration, photonic communication, low-power mapping techniques, and low-latency adaptive routing.

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We are actively researching anthropomorphic prosthetics and androids, integrating cutting-edge neuroscience, artificial intelligence, and robotics to develop highly responsive, lifelike systems that enhance both human mobility and interaction. Through neuromorphic computing and spiking neural networks, we strive to achieve more natural, intuitive control, ensuring seamless communication between artificial limbs, androids, and biological systems.
Our focus on non-invasive neural interfaces enables prosthetics to adapt dynamically to user intent, enhancing precision, comfort, and fluidity of motion. Meanwhile, our research on advanced sensory processing for androids aims to equip robotic entities with human-like awareness, allowing them to engage in complex tasks, interpret environmental stimuli, and interact intelligently with users. By bridging the gap between biomechanical engineering and AI-driven cognition, we are paving the way for next-generation assistive technologies and autonomous systems that are deeply integrated into daily life. Our work contributes to advancements in rehabilitation, human augmentation, and adaptive robotics, revolutionizing the way artificial systems complement and extend human capabilities.

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We are exploring the development of an adaptive ultra-low power neuromorphic chip (NASH) and systems, enhanced by our previously developed fault-tolerant three-dimensional on-chip interconnect technology. The NASH system boasts several features, including an efficient adaptive configuration method that enables the reconfiguration of various SNN parameters such as spike weights, routing, hidden layers, and topology. Additionally, the system incorporates a blend of different deep neural network topologies, an efficient fault-tolerant multicast spike routing algorithm, and an effective on-chip learning mechanism. To demonstrate the performance of the NASH system, we will develop an FPGA implementation and establish a VLSI implementation. The ultimate goal of NASH is to bring brain-inspired processing technology to small-scale embedded sensors and sensor-based devices, such as BCI (EEG/EMG), audio, presence detection, and activity recognition.

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